This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-205422, filed Jul. 6, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a solid-state imaging system using a solid-state imaging device and, more specifically, to a solid-state imaging system using a solid-state imaging device of an amplification type provided with a charge detecting circuit for each pixel or cell, which may be used in video cameras and electronic still cameras.
2. Description of the Related Art
Solid-state imaging devices include CCD (charge coupled device)-based solid-state imaging devices and amplification type solid-state imaging devices provided with a charge detecting device for each pixel. To increase the dynamic range, two main approaches have been adopted: one is to allow the photoelectric conversion characteristic to have nonlinearity, and the other is to use an operation of setting the integration time to be less than the frame rate (the time required to read out one frame), i.e., to employ the so-called electronic shutter function.
With conventional CCD solid-stage imaging devices, an electronic shutter operation using vertical overflow drains is often performed for improving the pixel aperture ratio. In such an electronic shutter operation, much structural difficulties are involved in setting different integration times to each pixel on the imaging surface; therefore, all the pixels are often allocated the same integration time. Thus, the integration time will be set so that the brightest pixel will not be saturated. In that case, an output of a pixel on which dim light falls will be buried in noise components because of its insufficient integration time, causing a problem that a sufficient signal-to-noise ratio in the entire image cannot necessarily be obtained.
In contrast, in the amplification type solid-state image device, unlike the CCD solid-stage imaging devices, the charge transfer operation is performed only in the periphery of photodiodes; thus, the power and voltage required of the charge transfer operation become unnecessary and they are suited for use in mobiles which are operated from batteries.
FIGS. 8A and 8B show a schematic arrangement of a conventional amplification type solid-state imaging device. In this exemplary arrangement, one photodiode forms one unit cell.
In FIGS. 8A and 8B, Sj denote vertical signal lines, Ij, current sources, SHj, shift gates, CAj and CBj, capacitances for signal processing, CLPj, clamping gates for removing offset, Hj, line readout gates, LHj, line readout pulse lines, xcfx86Hj, line readout pulses, LADi, address pulse lines, xcfx86ADi, address pulses, LRi, readout pulse lines, xcfx86Ri, readout pulses, LRSi, reset pulse lines, xcfx86RSi, reset pulses, LSH, a shift pulse line, xcfx86SH, a shift pulse, LCLP, a clamp pulse line, xcfx86CLP, a clamp pulse, LCR, a clear pulse line, and xcfx86CR, a clear pulse.
In addition, 20 denotes a pulse generator that generates the pulses xcfx86Di, xcfx86Ri, and xcfx86RSi; 21, a pulse generator that generates the pulses xcfx86SH and xcfx86CLP; 23, a clamping DC power supply; 24, a horizontal signal line; 25, a capacitor attached to the horizontal signal line 24; 26, an output buffer circuit that detects the potential on the horizontal signal line and outputs the detected potential with impedance conversion; 27, an output node; 28, a gate for resetting the potential at the capacitor 25; and 29, a power supply for generating a potential at the reset time. The output voltage of the power supply 29 (assumed to be Vb) is set with the characteristic of the output buffer circuit 26 taken into account. A clear pulse xcfx86CR is applied to the gate 28 before each of the line readout pulses xcfx86Hj is applied to a corresponding one of the line readout gates Hj with the result that the capacitor 25 is fixed at Vb.
The horizontal pulse generator 22 generates the pulses xcfx86Hj and xcfx86CR so that the imaging device is driven to perform a normal horizontal line read operation within each horizontal line period, as shown in FIG. 9.
In the imaging area on the semiconductor substrate, unit cells Pij are two-dimensionally arrayed in m columns and n rows, the subscript i being the row number from 1 to m and j being the column number from 1 to n. For each row of the unit cells, an address pulse line LADi, a readout pulse line Lri and a reset pulse line LRSi are provided in the horizontal direction. Each unit cell Pij is connected to a pulse generator 20 as vertical driving means to receive an address pulse xcfx86ADi, a readout pulse xcfx86Ri, and a reset pulse xcfx86Rsi over the three pulse lines (the address pulse line LADi, the readout pulse line Lri, and the reset pulse line LRSi). For each column of the unit cells Pij, a vertical signal line Sj is provided in the vertical direction. Each unit cell Pij has its output line 8 connected to a corresponding one of the vertical signal lines Sj.
As previously described, the horizontal pulse generator 22 generates the pulses xcfx86Hj and xcfx86CR so that the imaging device is driven to perform a normal horizontal line read operation within each horizontal line period, as shown in FIG. 9.
FIG. 9 illustrates the conventional timing of pulse signals for driving the solid-state imaging device of FIGS. 8A and 8B using a system of non-interlaced scanning.
In this diagram, HBLK denotes a horizontal sync pulse signal the high-level interval of which indicates the horizontal line blanking period. The interval when HBLK is low is the line effective scanning period, during which line readout pulses xcfx86Hj are produced. The line blanking period and the line effective scanning period form one line scanning period (1H). In the line scanning period, a signal is read from each unit cell during the line blanking period and stored in the form of charge at the corresponding capacitor CBj. After that, the line readout transistors Hj are turned on in sequence to connect capacitors 25 and CAj, CBj in parallel to read the stored signal charges.
Next, the read operation of the unit cells Pij will be described in detail with reference to the timing diagram shown in FIG. 9.
Charges produced as a result of photoelectric conversion of light incident on the photodiode 1 are stored in it until the readout transistor 2 is turned on. In the line blanking period, first, at time t=t0, the address pulse xcfx86ADi is set high to turn the address transistor 6 on, thus forming a source follower circuit from the vertical signal line Sj, the current source Ij, and the potential detecting transistor 5 so as to allow the transistor 5 to detect charges at the storage node 3. Thereby, only the potential determined by the gate potential of the transistor 5 corresponding to the amount of charge at the storage node 3 is transferred to the vertical signal line Sj.
At the beginning of the line blanking period, the reset pulse xcfx86Rsi is set high to turn the reset transistor 4 on, which allows the amount of charge resulting from integration of dark current at the storage node 3 to be drained away at the beginning of the line blanking period. Thereby, the storage node 3 is set at the supply voltage (Vdd).
When the amount of charge Qij has been transferred from the photodiode 1 to the storage node 3, the potential V3ij at the storage node is given by
V3ij=Vdd+Qij/Cijxe2x80x83xe2x80x83(1) 
where Cij is capacitance associated with the storage node and Vdd is the supply voltage.
The potential V3ij is detected by the potential detecting transistor 5, so that the potential V8ij on the output line 8 becomes
V8ij=mV3ij+Voij 
=m(Vdd+Qij/Cij)+Voij 
=mQij/Cij+mVdd+Voijxe2x80x83xe2x80x83(2) 
where m is the modulation factor of the transistor (gate) 5 and Voij is the offset voltage determined by variations in the threshold voltage of the transistor 5 and the current source Ij.
With current manufacturing techniques, the modulation factor m can be formed with little variation over the entire wafer, and thus, the modulation factor m may be considered to be approximately constant. However, this is not the case with the offset voltage Voij, which varies from vertical signal line to vertical signal line. Accordingly, the offset voltage needs to be corrected.
Let the voltage of the DC power supply 23 be Vref and consider the potential V8ij on the output line 8 and the potential Vaj at the node Aj to which the capacitors CAj and CBj in the noise canceling circuit are connected together. Let V8ij at time t=t1 immediately after resetting be
V8ij=mVdd+Voij=V1xe2x80x83xe2x80x83(3) 
At time t=t2 immediately after application of the clamp pulse xcfx86CLP, the potential V8ij on the output line 8 remains unchanged from V1, but VAj becomes
VAj=Vrefxe2x80x83xe2x80x83(4) 
That is, a potential difference of Vrefxe2x88x92V1 is produced across the capacitor CAj. The plate of the capacitor CBj opposite to its grounded plate is at Vref. Next, the readout pulse xcfx86Ri is set high to turn the readout transistor 2 on, so that the charges Qij stored in the photodiode 1 are transferred to the storage node 3. As a result, at time t=t3, V8ij becomes
V8ij=mQij/Cij+V1xe2x80x83xe2x80x83(5) 
Thus, the potential Vaj at the node Aj is set at
VAj=Vref+(mQij/Cij)CAj/(CAj+CBj)xe2x80x83xe2x80x83(6) 
After that, the shift pulse xcfx86SH is set low to turn the shift transistors SHj off and thereby disconnect the vertical signal lines Sj. The horizontal sync pulse HBLK is then set low. In this state (t=t4), let the amount of charge stored at the capacitors 25 and CBj be Q1 and Q2j, respectively. Then, Q1 and Q2j are given by
Q1=CHxc2x7Vbxe2x80x83xe2x80x83(7) 
Q2j=CBjxc2x7Vref+(mQij/Cij)CAjxc2x7CBj/(CAj+CBj)xe2x80x83xe2x80x83(8) 
where CH is the capacitance of the capacitor 25 and Vb is the voltage of the power supply 29.
After that, in the interval when the horizontal sync pulse HBLK is low, the line readout pulse xcfx86Hj is set high subsequently to setting the clear pulse xcfx86CR high to turn the line readout transistor Hj on. Since the capacitors are paralleled, the potential on the horizontal signal line 24 becomes
(Q1+Q2j)/(CH+CBj)=(CHxc2x7Vb+CBjxc2x7Vref)/(CH+CBj)+(mQij/Cij)CAjxc2x7CBj/(CAj+CBj)(CH+CBj)xe2x80x83xe2x80x83(9) 
As can be seen from equation (9), the potential on the horizontal signal line 24 contains components CAj and CBj that may vary from column to column and a component Cij that may vary from cell to cell, the other components being independent of rows and columns. In other words, Voij that may vary with the threshold voltage and so on is not contained, indicating an effective correction on the potential V8j on the output line 8.
Further, closer examination of equation (9) shows that it does not depend on the absolute values of capacitances but on their ratio except for the term of mQij/Cij. This shows that the output voltage does not depend on the absolute values of the thickness of gate oxides but is determined by the geometrical size ratio among capacitor patterns, which means that the variations in the output voltage can be reduced relatively readily by current manufacturing techniques. The modulation factor m of transistors, which is a variable that can be controlled relatively readily, can be set with little variation and may be considered to be nearly constant. Eventually, therefore, only Cij that may vary from cell to cell will have some effect on the output voltage.
By setting each of the horizontal readout pulses xcfx86H1, xcfx86H2, xcfx86H3, high in sequence with each application of the clear pulse xcfx86CR during the low-level period of the horizontal sync pulse HBLK, signals are obtained in time sequence from the output node 27 via the horizontal signal line 24, thereby producing a line of video information.
However, no specific approach to increase the dynamic range for each line (row) in the amplification type solid-state imaging device has been presented heretofore.
According to a first aspect of the present invention there is provided a solid-state imaging system comprising: a solid-state imaging device having an imaging area in which unit cells are arrayed in rows and columns on a semiconductor substrate, each unit cell having a photoelectric conversion storage element for converting an incident light into the form of electric charge and storing the produced charge, a charge readout element for readout the charge stored in the photoelectric conversion storage element, a charge detecting element for detecting the amount of charge readout by the charge readout element, and an address element for activating the charge detecting element;
a vertical driving circuit for driving the charge readout element and the address element of the unit cells for each row of unit cells; signal processing circuits each provided for a respective one of vertical signal lines each arranged for a respective one of the columns of unit cells; horizontal line readout switches each provided for a respective one of the vertical signal lines, for controlling a transfer of an output signal of the corresponding signal processing circuit to a horizontal signal line; a horizontal driving circuit for controlling the horizontal line readout switches to allow the transfer of output signals of the signal processing circuits to the horizontal signal line; and an output circuit for outputting the output signals of the signal processing circuits read out onto the horizontal signal line under the control of the horizontal driving circuit, the solid-state imaging device having an operation mode in which the horizontal driving circuit turns on the horizontal readout switches at substantially the same time so that output signals of the signal processing circuits read out through the switches onto the horizontal signal line are averaged to form a signal of an average level for each row of unit cells and the signal of the average level is outputted from the output circuit, the integration time of the photoelectric conversion storage element in the unit cells or the amplifier gain for the output of the output circuit being set for each row of unit cells on the basis of the average level of the output signal outputted from the output circuit in the operation mode.
In the solid-state imaging system according to the first aspect of the present invention, the integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
According to a second aspect of the present invention, there is also provided a solid-state imaging system comprising: a solid-state imaging device having an imaging area in which unit cells are arrayed in rows and columns on a semiconductor substrate, each unit cell having a photoelectric conversion storage element for converting an incident light into the form of electric charge and storing the produced charge, a charge readout element for readout the charge stored in the photoelectric conversion storage element, a charge detecting element for detecting the amount of charge readout by the charge readout element, and an address element for activating the charge detecting element; a vertical driving circuit for driving the charge readout element and the address element of the unit cells for each row of unit cells; signal processing circuits each provided for a respective one of vertical signal lines each arranged for a respective one of the columns of unit cells; horizontal line readout switches each provided for a respective one of the vertical signal lines, for controlling a transfer of an output signal of the corresponding signal processing circuit to a horizontal signal line; a horizontal driving circuit for controlling the horizontal line readout switches to allow the transfer of output signals of the signal processing circuits to the horizontal signal line; and an output circuit for outputting the output signals of the signal processing circuits read out onto the horizontal signal line under the control of the horizontal driving circuit, the solid-state imaging device having a first operation mode in which the horizontal driving circuit turns on the horizontal readout switches in sequence during an effective scanning period in a horizontal line period so that the output signals of the signal processing circuits are outputted in sequence through the horizontal signal line from the output circuit and a second operation mode in which the horizontal driving circuit turns on the horizontal readout switches at substantially the same time during the blanking period subsequent to the effective scanning period so that output signals of the signal processing circuits read out through the switches onto the horizontal signal line are averaged to form a signal of an average level for each row of unit cells and the signal of an average level is outputted from the output circuit; and a storage circuit for storing data of the average level of the signal in the second operation mode outputted from the output circuit for each row of unit cells, the integration time of the photoelectric conversion storage element in the unit cells being set for each row of unit cells on the basis of the average level of the signal in the second operation mode.
In the solid-state imaging system according to the second aspect of the present invention, the integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
In the solid-state imaging system according to the second aspect of the present invention, the integration time in each row of unit cells in the solid-state imaging device may be set based on the average level of the signal in the second operation mode for that row in the second operation mode in the immediately preceding frame period. The integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
According to a third aspect of the present invention, there is further provided a solid-state imaging system comprising: a solid-state imaging device having an imaging area in which unit cells are arrayed in rows and columns on a semiconductor substrate, each unit cell having a photoelectric conversion storage element for converting an incident light into the form of electric charge and storing the produced charge, a charge readout element for readout the charge stored in the photoelectric conversion storage element, a charge detecting element for detecting the amount of charge readout by the charge readout element, and an address element for activating the charge detecting element; a vertical driving circuit for driving the charge readout element and the address element of the unit cells for each row of unit cells; signal processing circuits each provided for a respective one of vertical signal lines each arranged for a respective one of the columns of unit cells; horizontal line readout switches each provided for a respective one of the vertical signal lines, for controlling a transfer of an output signal of the corresponding signal processing circuit to a horizontal signal line; a horizontal driving circuit for controlling the horizontal line readout switches to allow the transfer of output signals of the signal processing circuits to the horizontal signal line; and an output circuit for outputting the output signals of the signal processing circuits read out onto the horizontal signal line under the control of the horizontal driving circuit, the solid-state imaging device having a first operation mode in which, in a normal frame, the horizontal driving circuit turns on the horizontal readout switches for each row of unit cells in sequence during an effective scanning period in a horizontal line period so that the output signals of the signal processing circuits are outputted in sequence through the horizontal signal line from the output circuit and a second operation mode in which, in a preliminary frame, the horizontal driving circuit turns on the horizontal readout switches at substantially the same time for each row of unit cells so that output signals of the signal processing circuits read out through the switches onto the horizontal signal line are averaged to form a signal of an average level for each row of unit cells and the signal of an average level is outputted from the output circuit; and a storage circuit for storing data of the average level of the signal in the second operation mode outputted from the output circuit for each row of unit cells, the integration time of the photoelectric conversion storage element in the unit cells in each row of unit cells in the first operation mode on the basis of the average level of the signal in the second operation mode for that row in the second operation mode in the preliminary frame followed by the normal frame.
In the solid-state imaging system according to the third aspect of the present invention, the integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
In the solid-state imaging system according to the third aspect of the present invention, the period of the preliminary frame may be set shorter than that of the normal frame. The integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
According to a fourth aspect of the present invention, there is further provided a solid-state imaging system comprising: a solid-state imaging device having: an imaging area in which unit cells are arrayed in rows and columns on a semiconductor substrate, each unit cell having a photoelectric conversion storage element for converting an incident light into the form of electric charge and storing the produced charge, a charge readout element for readout the charge stored in the photoelectric conversion storage element, a charge detecting element for detecting the amount of charge readout by the charge readout element, and an address element for activating the charge detecting element; a vertical driving circuit for driving the charge readout element and the address element of the unit cells for each row of unit cells; signal processing circuits each provided for a respective one of vertical signal lines each arranged for a respective one of the columns of unit cells; horizontal line readout switches each provided for a respective one of the vertical signal lines, for controlling a transfer of an output signal of the corresponding signal processing circuit to a horizontal signal line; a horizontal driving circuit for controlling the horizontal line readout switches to allow the transfer of output signals of the signal processing circuits to the horizontal signal line, and an output circuit for outputting the output signals of the signal processing circuits read out onto the horizontal signal line under the control of the horizontal driving circuit, the solid-state imaging device having a first operation mode in which the horizontal driving circuit turns on the horizontal readout switches in sequence during an effective scanning period in a horizontal line period so that the output signals of the signal processing circuits are outputted in sequence through the horizontal signal line from the output circuit and a second operation mode in which the horizontal driving circuit turns on the horizontal readout switches at substantially the same time so that output signals of the signal processing circuits read out through the switches onto the horizontal signal line are averaged to form a signal of an average level for each row of unit cells and the signal of the average level is outputted from the output circuit; an amplifier for amplifying output signals in the first operation mode outputted from the output circuit; and a storage circuit for storing data of the average level of the signal in the second operation mode outputted from the output circuit for each row of unit cells, the gain of the amplifier being set for each row of unit cells on the basis of the signal of the average level in the second operation mode.
In the solid-state imaging system according to the fourth aspect of the present invention, the integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
In the solid-state imaging system according to the fourth aspect of the present invention, the second operation mode may be carried out during the blanking period subsequent to the effective scanning period, and when amplifying output signals from each row of unit cells in the first operation mode in the amplifier, the gain of the amplifier may be set based on the signal of the average level in the second operation mode for the adjacent row of one row before that row in the same frame. The integration time for each row of unit cells may be set based on a value obtained by correcting the corresponding average output level in the second operation mode according to a predetermined compression characteristic.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.